A Low Noise, Low Power Phase-Locked Loop, Using Optimization Methods
نویسندگان
چکیده
منابع مشابه
Low Jitter Phase-Locked Loop
For high speed application, jitter is a problem to communication system, as it reduces the performance of overall circuitry. As jitter is a type of corruption that cannot be eliminated, reducing jitter is one way to help to improve the system performance. In this paper, we introduce some ways to reduce the jitter in phase-locked loop. Introduction Phase-Locked Loop, PLL, is widely used among th...
متن کاملDesign of Low Phase Noise Low Power CMOS Phase Locked Loops
Phase locked loop (PLL) is one of the most critical devices in modern electronic systems. PLLs are widely used as clock generator or frequency synthesis in communication systems, computers, radio and other electronic applications. Phase noise represents the phase variations of a PLL output signal and is the most important characteristic of PLLs because it reflects the stability of PLL systems. ...
متن کاملA 4.9-GHz Low Power, Low Jitter, LC Phase Locked Loop
This paper presents a low power, low jitter LC phase locked loop (PLL) which has been designed and fabricated in a commercial 0.25-μm Silicon-on-Sapphire CMOS technology. Random jitter and deterministic jitter of the PLL are 1.3 ps and 7.5 ps, respectively. The measured tuning range, from 4.6 to 5.0 GHz, is narrower than the expected one, from 3.8 to 5.0 GHz. The narrow tuning range issue has b...
متن کاملA Low Phase Noise Ring Oscillator Phase-Locked Loop for Wireless Applications
This thesis describes the circuit level design of a 900MHz EA ring oscillator based phase-locked loop using 0.35um technology. Multiple phase noise theories are considered giving insight into low phase-noise voltage controlled oscillator design. The circuit utilizes a fully symmetric differential voltage controlled oscillator with cascode current starved inverters to reduces current noise. A co...
متن کاملDesign and Implementation of Low Ripple Low Power Digital Phase-Locked Loop
We propose a phase-locked loop (PLL) architecture which reduces double frequency ripple without increasing the order of loop filter. Proposed architecture uses quadrature numerically–controlled oscillator (NCO) to provide two output signals with phase difference of π / 2 . One of them is subtracted from the input signal before multiplying with the other output of NCO. The system also provides s...
متن کاملذخیره در منابع من
با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید
ژورنال
عنوان ژورنال: Journal of Electrical and Computer Engineering
سال: 2016
ISSN: 2090-0147,2090-0155
DOI: 10.1155/2016/8202581